The present invention generally relates to ESD (Electro-Static Discharge) protection devices in integrated-circuit chip designs, and more specifically relates to low-voltage trigger NMOS fingers.
Grounded-gate NMOSFET's (ggNMOSFET's) are widely used as the power pin ESD (Electro-Static Discharge) protection device in integrated-circuit chip designs. A cross-sectional diagram of a typical four-finger ggNMOSFET is shown in FIG. 1, wherein reference numerals 10 identify the fingers. The ggNMOSFET is triggered by turning-on parasitic bipolar transistors 24 due to avalanche breakdown with the generation of electron-hole pairs. In FIG. 1, reference numerals 14 identify VSSIO interconnects, reference numerals 16 identify VDD interconnects, and reference numerals 18 identify shallow trench isolation (“STI”) regions.
The P-well 20 is formed on a P-conductivity type substrate 22. To trigger the parasitic bipolar transistors 24, the effective P-Well resistance 26 plays an important role because of building-up the potential at the source to P-Well junction 28. However, the doping concentration of the P-well 20 is usually much higher than that of the resistance of the P-substrate 22, so the effective P-Well resistance 26 is relatively low. As CMOS technology scales down in the semiconductor industry, gate-oxide thickness decreases (e.g., 20 Angstroms in 0.13 μm node technology), as well as junction depth. Therefore, the ESD design window is narrowed because the triggering voltage of ggNMOSFET's is very close to the voltage level at which the oxide breaks down. It becomes especially difficult to protect ESD protection devices in power-crossing circuitry, e.g., in digital-to-analog or analog-to-digital interface circuits. To lower the triggering voltage of ggNMOSFET's, U.S. Pat. No. 6,469,354 proposes providing a high impedance region between ggNMOSFET's and VSS P-well taps to trigger the parasitic bipolar transistors below avalanche breakdown due to the high resistance of the P-substrate. However, this approach cannot be a universal solution in CMOS technology because, unless an additional P/N junction diode is provided, ESD protection degrades in the case of negative zapping, due to the high-impedance region. Additionally, triggering voltage cannot be lowered too substantially in the case of high avalanche breakdown junction design.
In C. Duvvury & A. Amerasekera, Advanced CMOS Protection Device Trigger Mechanisms During CDM, 1995 EOS/ESD Symposium (EOS-17), pp. 162–174, gate-coupled NMOS fingers were designed to lower the triggering voltage by using an external capacitor and an external resistor. However, this gate-coupled device usually needs a large layout area, and thus is not feasible.